What are the main software products of the three major EDA companies?   

Why can't the chip design industry break away from EDA tools?

I don't know if anyone still remembers this photo. On March 3, 2017, at the end of the conference of Xiaomi 5C mobile phone and Xiaomi's own SoC chip Surging S1, Lei Jun announced this thank you picture.

The red box in the picture is the three giants in the EDA field: Synopsys, Cadence, Mentor, and the green box is our domestic EDA company Huada Jiutian. In my impression, this is the first time that EDA has appeared at the launch site of consumer electronics products.

Almost all of the three giants can provide full-process tools for chip design, but Synopsys has the advantage of digital chips and FPAG logic synthesis related tools. Its logic synthesis tool DesignCompiler, static timing analysis tool PrimeTime, and debugging tool Verdi have a near monopoly position in the industry. In June 2019, Synopsys also launched more advanced tools at SNUG2019; Cadence has absolute advantages in analog IC full-process tools, and Innovus, its digital placement and routing tool in recent years, has gained a very good market share; Mentor It has been acquired by Siemens in Germany. Although it is relatively weak in the whole process, Calibre signoff and DFT are outstanding.

Chip design is a field with extremely high barriers to entry. It has extremely strict requirements on product reliability and historical reputation. Any small error in the virtual simulation stage may cause chip tape-out failure, which means several years of work. Destroyed, the company faced the tragic situation of market fall. Therefore, in the field of chip design, almost no EDA company in the world has the strength to wrestle with the three giants. In the field of EDA, the most successful outcome of entrepreneurship is to be acquired by the above three giants.

Therefore, the EDA tools of the three giants are almost the only choice for Fabless.

Where is the difficulty in researching EDA tools?

As mentioned above, the chip design process is numerous, delicate and complex, and EDA tools play an extremely important role in it: ① The complex physical problems are expressed with a high degree of precision in mathematical models, and various processes in the chip manufacturing process can be reproduced in virtual software. Physical effects and problems; ② On the premise of ensuring the correct logic function, use mathematical tools to solve the multi-objective multi-constraint optimization problem, and obtain the optimal performance, power consumption, area, electrical characteristics, cost, etc. under specific semiconductor process conditions. Optimal solution; ③Verify the model consistency problem to ensure that the logic function of the chip is consistent in the iterations of multiple design links.

(1) Advanced process nodes: the results of the collaborative promotion of "fab + Fabless + EDA"

First, the invention of new device structures such as SOI and FinFET will bring about changes in the electrical and physical properties of transistors; secondly, in terms of semiconductor process manufacturing, the evolution of Moore's Law is accompanied by many unpredictable physical problems. The fabs at the forefront of Moore's Law are innovating, debugging and verifying various manufacturing details such as materials, chemistry, and process control. EDA, on the other hand, uses the vast amount of test data accumulated by the fab to explore accurate and high-precision modeling of physical effects and process implementation details. However, this does not mean the end of the research and development of new process nodes. Top Fabless companies will conduct chip design and trial production based on this model and tool, and rely on powerful and rich chip designs to continuously discover and exclude new process nodes in model and manufacturing. various mass production issues. During this period, chip design engineers, AEs of EDA companies, fab engineers, etc. often worked together for many years, focusing on breaking new problems and fixing new bugs. The fab, Fabless, and EDA work together and iterate repeatedly, so that the process nodes that meet the commercial and mass production requirements can finally be brought to the market. Once there is a question in a link, all previous efforts will be lost.

Therefore, any generation of the most advanced process nodes in Moore's Law is the result of the joint efforts of the fabs with the most advanced process manufacturing conditions, the top EDA team and the Fabless company with rich design experience. This is why the first products of TSMC's most advanced process are always released by Apple, Qualcomm, and Huawei, and only top Fabless companies have the ability to participate in debugging the most advanced process nodes. This is also an important reason why the three major EDA giants always control the market segment.

(2) Mathematical problems

Taking the classic interconnection deviation problem in the process of an aluminum interconnection era as an example, when the aluminum interconnection is formed, the silicon dioxide layer is sandwiched between the metal layers of the interconnection pattern, and the oxide is deposited on the formed metal. On the layer, some step heights or surface topography are generally left. In an ideal case, the thickness of the interlayer dielectric is flattened by the CMP method, as shown in Figure a.

But the actual situation is that although a high flatness can be achieved within a specific range, the flatness is very limited in terms of the entire chip range. As shown in the figure, different thicknesses have different effects on the capacitance and other electrical properties of the dielectric. Impact.

What EDA tools do is to re-fit and fit real-world physical and process problems like the above in the virtual software world with as high a precision as possible, with the expectation that they will be taken into account during the chip design phase to systematically Methods and predictive margins are used to respond and correct, and ultimately ensure that the chip design simulation results are consistent with the tape-out results.

At the same time, EDA tools need to quickly design and explore thousands of scenarios to achieve a balance between chip physical indicators such as performance, power consumption, area, and cost and economic indicators. With the integrated circuit manufacturing process entering below 7nm, the number of standard cells in digital chips has reached the order of 100 million, and the EDA algorithm has become a typical representative of typical data-intensive computing. In addition, most of the existing layout and routing methods use combinatorial optimization algorithms. In an acceptable calculation time, a local optimal solution may not be obtained, and even an inferior solution may be obtained, and the algorithm complexity is high. The above two points result in a very lengthy calculation time of the EDA algorithm, measured in hours.

Taking a simple schematic diagram of the routing algorithm as an example, the following animation shows the metal routing scheme of the EDA tool seeking between the source point and the end point. Imagine that the number of internal units in the chip is in the order of 100 million, and the internal wiring metal layers are as many as several layers. How to go through various obstacles that cannot be routed from a point and continue to make progress under the limitation of only walking in straight lines and 90-degree turns? The decision of the line, through the layers of metal, is finally ready to reach another point in the chip, during which the computational space requirements of the exploration scheme are huge, and the overall goal of minimum timing and bus length must be met, and the above mentioned must be considered. Process deviation.

(3) Interdisciplinary personnel training of semiconductors, mathematics, and chip design.

The starting point and end point of the EDA algorithm problem are physical problems such as semiconductor technology, the solution tool is a mathematical problem, and the application object is the specific problem of chip design and implementation. Generally speaking, it is difficult for undergraduates to have such a broad and specific knowledge reserve and system. Therefore, the average academic qualifications of R&D engineers in the three major EDA companies are very high. At the same time, at the master's and doctoral levels, there are many people who are solely engaged in mathematics, chip design, semiconductor devices and processes, but very few people have both.

Currently, only a few schools in my country, such as Tsinghua University, Fudan University, Zhejiang University, Beihang University, University of Electronic Science and Technology of China, Xidian University, Fuzhou University, are engaged in EDA research and personnel training. In particular, the Department of Computer Science of Tsinghua University started related research in the 1970s, made great contributions to the research and development of my country's domestic panda EDA tools (predecessor of BGI) and BGI Jiutian EDA tools, and cultivated a large number of EDA algorithm talents.

It is gratifying that the R&D strength of domestic EDA has also made great progress in recent years. In June 2017, at the 54th Design Automation Conference (ACM/IEEE Design Automation Conference 2017), the flagship conference in the field of integrated circuit computer-aided design, the paper Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs by Professor Chen Jianli of Fuzhou University Won the Best Paper Award (authors: Jianli Chen, Ziran Zhu, WenxingZhu,Yao-wen Chang). This is the first time in 54 years that an author from mainland China has won the best paper award at the conference as the first unit/first author.

As mentioned in the first section of this article, domestic EDA tools are still mainly point tools, and only BGI Jiutian has a full-process tool for analog IC design. However, there are also bright spots. In the past few years, BGI's Xtime physical design timing optimization and sign-off tools and solutions have been well received by first-line engineers in the industry, and have successfully entered the world's first-class chip design companies, becoming a leader in the digital process. important part. Moreover, BGI Jiutian is the only provider in the world that can provide full-process EDA design solutions for LCD flat panel displays, with a domestic market share of over 90%.

Under this predicament, domestic EDA tools will enter the field of view of domestic Fabless, gain an opportunity to expand market share, and then obtain the opportunity to cooperate with wafer fabs with advanced manufacturing process, and the first year of domestic EDA may begin with this.

Note: This article was originally published on Zhihu on June 3, 2019, and was reposted with the authorization of the original author.

【About the Author】

Di Zhixiong, Ph.D., is the deputy director of the Department of Electronics, School of Information, Southwest Jiaotong University. His research interests include physical implementation algorithms for digital chips and high-performance image codec chip design.

Presided over the National Natural Science Foundation of China, key projects of the Sichuan Provincial Department of Science and Technology, etc., and participated in the completion of the first aerospace-grade high-speed image compression chip "Yaxin-Tiantu" independently developed by my country (which has been applied to the "Chang'e" series of lunar exploration projects, etc.); Published many papers in IEEE GRSL, IEEE TCAS2, IEEE TIE, GLS-VLSI, Chinese Journal of Electronics, etc.; won the 2020 "Zhan Tianyou-Teaching and Educating People Award", and the 2021 Alibaba Cloud 16th MVP; lectured on the MOOC course "Hardware Acceleration" Design Method”, with more than 10,000 students enrolled in courses; 20 national awards for guiding students in science and technology innovation competitions.